Data Converters for High Speed CMOS Links A PhD Thesis

The long links that interconnect networking and computing systems and boards need high throughput to avoid expensive, massively parallel connections. However, long wires suffer signal losses that increase with frequency. Digital communication techniques can compensate for these losses, but require Analog-to-Digital and Digital-to-Analog converters (ADCs and DACs). To understand the application of these techniques to high speed links, an 8 GSample/sec CMOS transceiver chip is designed to explore the limits of high speed data converter performance. The transceiver chip provides a high bandwidth signal path and precision clocks, despite the large parasitic capacitances and transistor matching errors of CMOS technology. Small, high bandwidth sample-and-hold amplifiers are used in the ADC, and the resulting large mismatch errors are corrected by small DACs in each comparator. Other circuit and signal degradations such as transmitter nonlinearity, clock coupling, and static phase errors are also digitally corrected. Time interleaving is used to achieve 8GSa/s, and the effects of the increased data converter capacitances are reduced with bond-wire inductors. These inductors distribute the lumped parasitic capacitances at the transceiver input and output to approximate distributed 50Ω transmission lines, reducing attenuation by 10 dB at 4 GHz. Equalization algorithms using the converters compensate for the 3 GHz transceiver bandwidth to allow 8GSa/s multi-level data transmission. Measured results indicate that digitally corrected data converters will allow digital communication techniques to be applied to high speed CMOS links.